On the occasion of Embedded World 2007 in Nuremberg and Bus&Boards 2007 in the USA MEN Mikro Elektronik is going to introduce a forward-looking further development for the two most popular mezzanine standards.
The “USM Universal Submodule” concept is leading the way to a new generation of M-Modules and PMCs that implement the desired functionality through an IP core in an FPGA. With the help of a comprehensive USM development package the user can turn very special I/O requirements into series products in a fast and easy way.
FPGA Technology Unites M-Modules and PMCs
USM Universal Submodules make common mezzanine modules more flexible than ever. A “base PMC” or “base M-Module” gets its specific function through the IP cores implemented inside the FPGA. This function can be changed at any time through implementation of different IP cores. The corresponding line drivers are realized on the USM (Universal Submodule). The USM is simply plugged on the respective base PMC or base M-Module.
The same USM may be used on M-Modules, PMC modules or XMCs and conduction-cooled PMC modules. A new design is then limited to the USM module and the FPGA content and therefore saves development time and costs. The Nios soft processor implemented in the Cyclone II FPGA by Altera provides local intelligence where needed. I/O signals are led to a SCSI connector at the front.
USM Development Package Supports Time-to-Market
Users who want to develop their own I/O inside the FPGA can now use a USM development package for M-Modules or PMC modules. The kit includes a base M Module (M199 equipped with an FPGA, 32MB DRAM and 8MB Flash) or a base PMC module (P599 equipped with an FPGA, 32MB DRAM and 2MB Flash). In addition the package includes a USM plug-on module in wire-wrap technique, a test board where I/O signals from the FPGA are led to and where a debug interface for the Nios soft core is implemented, a SCSI cable for connection between the base module and test board as well as an FPGA package.
The FPGA package comprises the Nios processor, memory control, connection to the PMC or M-Module, and the Avalon/Wishbone bridges. For development of IP cores on the standard Wishbone bus the Wishbone Bus Maker tool from MEN is included. In order to use the Nios cores and to develop IP cores on the Avalon bus you also need Altera’s Quartus II design environment including the SOPC builder.
Future-Proof Mezzanine Standards
Since I/O functions are realized in the FPGA the lifetime of a PMC module or M Module no longer depends on the availability of commercially available components. Even after 10 years and more IP cores that were once created can be brought into a new, and maybe larger FPGA, tailored to current needs.
Both M-Module and PMC base boards and the USM plug-on modules are designed for an operation temperature of -40 to +85°C. To meet demands for increased shock and vibration resistance the boards are equipped with soldered components and sturdy connectors.