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23 February 2006

Open Platform for Nios® II Applications on CompactPCI® - F206N

F206N – Hardware with ARM-class Soft Core

The F206N is a 3U CompactPCI card that has been designed around a Cyclone™ FPGA device to support the Altera Nios II processor. In FPGA, the Nios II processor provides similar performance to that of an ARM processor and hence fits into the lower end of MEN’s product range of CPU boards. An example of a typical application for the F206N could be an intelligent peripheral-slot card.

At the heart of the board, the Nios II processor and Cyclone FPGA provide a 33MHz, 32bit bus that is used to read and write to 32MB of SDRAM and 2MB of flash memory. The design of the board allows initial programming of the flash using a boundary scan interface. Once configured, the FPGA may be re-configured at any time during operation with data from the CompactPCI bus. The FPGA also controls four status LEDs and up to 83 user-defined I/O pins.

The final functionality of F206N depends entirely on the application and can be anything from a pure UART solution, up to a complex analog front end with DSP-like data preprocessing. Developers can use IP cores from MEN to deliver the functionality. The MEN product offering includes a range of different serial interfaces from RS232 to intelligent HDLC protocols and fast Ethernet. Other functions include graphics, fieldbus connections and digital I/O. Alternatively the Nios-CompactPCI development package, available with the board, allows the developers to create their own cores or to integrate cores from other third party vendors.

The F206N is designed for use in rugged environments. All of its components are specified for an operating temperature range of -40°C to +85°C and the board has no socketed components to enable it to be highly resistant to shock and vibration. In addition the card is supplied ready for coating so that it can be used in humid and dusty environments.

OPEN PLATFORM NIOS – COMPACTPCI

The combination of the F206N and the Nios-CompactPCI development package creates an open FPGA development platform. The package includes a sample design that contains a PCI system unit which integrates the standard Wishbone bus and the Altera Avalon bus.

The PCI system unit forms the interface to the PCI bus, where the F206N can then be addressed as a PCI slave. The system unit also connects to the Wishbone bus, where a SDRAM and flash controller have already been implemented. The user can now add any kind, and number of IP cores to the Wishbone bus. To do this MEN has developed a Wishbone bus-maker tool. The Wishbone-to-Avalon and Avalon-to-Wishbone bridges developed by MEN also allow the additional integration of Avalon-based IP cores, especially the Nios II soft processor. All the user needs to achieve this is the SOPC Builder tool that is delivered with the Quartus II development package from Altera.

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